1. Field of the Invention
The present invention relates to a frequency synthesizer, and more particularly, to a noise filtering fractional-n frequency synthesizer.
2. Description of the Prior Art
Conventional integer-N frequency synthesizers have very small channel spacings in general. To overcome this drawback, fractional-n frequency synthesizers have been developed, in which a divisor can be a fractional value and the synthesized frequency to be output may be a non-integer multiple of the reference frequency.
FIG. 1 shows a block diagram of a conventional fractional-n frequency synthesizer. The conventional fractional-n frequency synthesizer 100 comprises a phase frequency detector 101, a charge pump 102, a loop filter 103, a voltage-controlled oscillator 104, and a multi-modulus dividers 105. The conventional fractional-n frequency synthesizer 100 generates an output signal Sout based on an input signal Sref. The input signal Sref is generated by a clock source 110, which may be a crystal oscillator. The phase frequency detector 101 receives the input signal Sref and a feedback signal Sfb, compares the phase or frequency between them, and then sends a first switch signal Sup and a second switch signal Sdn to the charge pump 102. If the frequency of the feedback signal Sfb is lower than that of the input signal Sref, the charge pump 102 will charge the loop filter 103 to increase the input voltage Vctr1 which is input to the voltage-controlled oscillator 104, so that the frequency of the output signal Sout increases and thus causes the frequency of the feedback signal Sfb to increase accordingly. Similarly, if the frequency of the feedback signal Sfb is higher than that of the input signal Sref, the charge pump 102 will discharge the loop filter 103, and consequently, the frequency of the feedback signal Sfb will be reduced. Until after the phase frequency detector 101 detects that the frequency of the input signal Sref is equal to that of the feedback signal Sfb, the conventional fractional-n frequency synthesizer 100 will be locked. When it is locked, the frequency of the output signal Sout approximately equals the frequency of the input signal Sref divided by the divisor set in the multi-modulus dividers 105.
The main problem of a conventional fractional-n frequency synthesizer is that the divisor is a result of dynamic average; that is, a direct non-integer divisor cannot be realized. Therefore, a discrepancy exists between the actual instantaneous divisor generated and an ideal non-integer divisor. The result is that the output frequencies are in a state of dynamic balance when the fractional-n frequency synthesizer is locked, and the problem of quantization noise also rises.
A conventional fractional-n frequency synthesizer adopts a non-integral frequency divider which can dynamically switch between variable divisors, so that a non-integer divisor can be realized. However, a discrepancy exists between the actual instantaneous divisor generated and an ideal non-integer divisor. Moreover, since the divisor is variable, the phase of the signal fed back from the frequency divider to the phase frequency divider will also fluctuate. Thus, the phases of the feedback signal and the reference signal cannot be aligned, thereby causing the output frequencies in a state of dynamic balance when the fractional-n frequency synthesizer is locked. Although signals having a frequency of non-integer multiple are obtained, the phases of the feedback signal and the reference signal cannot be aligned.
Therefore, in comparison with a locked integral frequency divider, a non-integral frequency divider cannot really align the reference signal and the feedback signal; rather, only the average phase differences become close. This causes the quantization noise problems for fractional-n frequency synthesizers.
Quantization noise results from dynamic balance of the divisors, which makes the phases of the reference signal and the feedback signal unable to align. At the instant when the divisor varies, the phase will undergo a greater change. Thus, noise-filtering techniques are often adopted to suppress quantization noise by employing circuit arrangements to reduce the phase change.
However, how to reduce the phase change is a major problem. One of the conventional techniques utilizes a phase-locked loop, which acts as a low-pass filter in the phase domain, to connect serially to the output end of the frequency divider. Since the low-pass effect can be considered as generating an average of results, it would be better to generate at first an average of the phases for the signals output from the original frequency divider. This technique aims to reduce phase jitter and further reduce quantization noise.